dita-sidsc message
[Date Prev]
| [Thread Prev]
| [Thread Next]
| [Date Next]
--
[Date Index]
| [Thread Index]
| [List Home]
Subject: Component Specialization Ready for Eliot
- From: "Park Seth-R01164" <seth.park@freescale.com>
- To: <dita-sidsc@lists.oasis-open.org>
- Date: Wed, 3 Sep 2008 14:21:38 -0700
I've thoroughly
scrubbed the sidsc-component specialization. The changes that Tom Cihak made
were done properly. In the process of creating a basic XSLT override for the
DITA-OT plugin, I discovered many small issues (and a few major
ones).
Now everything seems
to be working as expected. I get good XHTML output, leveraging a healthy mix of
fall-back and custom stylesheet processing. Of course, that's what DITA is all
about!
The attached file is
in the plugin (which you can download from the OASIS site). It is the result of
running the sample (which is described in the README.html).
I am satisfied that
the specialization is ready for an Eliot review.
Regards,
Seth
--------------------------------------------
seth park
information architect
Freescale Semiconductor,
Inc.
512.895.2463
DITA IP-Component Preview
General Component Information for imask
Brief Description
interrupt mask block
Full Description
The imask block is used to enable IC's to
- mask interrupts
- unmask interrupts
Unit Address: 0x0000
Component Data Key: Address1
Component Data Value:0x5000
Memory Maps Information
Primary Memory Map
Bits in Lau: 8
Memory Map Class: Data
Address Blocks Information
Primary Address Block
Brief Description
This address block is where most of the registers are
found.
Full Description
When writing to this address block, it is important to understand that doing
so may over-write any work previously done to other address blocks. The
following table may not be helpful.
Table 1. Lesser Blocks
Name |
Over-write? |
A |
Yes |
B |
Yes |
C |
Yes |
Address Block Properties
Base Address:
0x0000 |
Range:
31:0 |
Width:
32 |
Byte Order:
H2L |
Registers Information
TMI
Too Much Information
Brief Description
The TMI registers indicate a TMI
condition
Full Description
Then the TMI registers indicate a TMI condition, plug the
information leak. If the TMI registers are a negative value, you may need to
increase the data rate
Register Properties
Bits in Lau:
8 |
Offset:
0x0C |
Size:
4 |
Access:
R/W |
Rest Value:
0xFFFF |
Bit Order:
bitOrder |
Reset Trigger:
HRESET_B |
Dimension Information
Dimension Value: dimVal
Dimension Increment: dimInc
|
Bit Fields Information
VALVE
Brief Description
Information Control Valve
Full Description
This bit determines whether information is allowed to
pass through the bus. Use this bit to control TMI conditions
Register Properties
Bit Numbers:
1 |
Bit Width:
1 |
Bit Offset:
0 |
Access:
RW |
Radix:
bfRad |
Reset:
0
Trigger: TMICB set
|
Source: System
Trigger: power-on-reset
|
0 |
clear |
information valve is open; TMI conditions
may ensue |
1 |
set |
information valve is closed; TMI
conditions can not occur |
[Date Prev]
| [Thread Prev]
| [Thread Next]
| [Date Next]
--
[Date Index]
| [Thread Index]
| [List Home]